Electrical memory circuits



Sept. 19, 1961 D. A. BUCK 3,001,178

ELECTRICAL MEMORY CIRCUITS Filed Deo. 9, 1957 v 2 sheets-sheet I Sept. 19, 17961 D, A, BUCK 3,001,178

ELECTRICAL MEMORY CIRCUITS Filed Dec. 9', 1957 2 sheets-sheet 2 United States @Patent 3,001,178 ELECTRICAL MEMORY CIRCUITS Dudley A. Buck, North Wilmington, Mass., assigner to Arthur D. Little, Inc., Cambridge, Mass., a corpora- .tion of Massachusetts Y Filed Dec. 9, 1957, Ser. No. 701,503

23 Claims. (Cl. S40-173.1)

This invention relates to electrical circuits for storing information and particularly to circuits utilizing superconducting materials.

Various superconductive materials are known which are capable of a change of state from one of finite electrical resistance to one of zero resistance. For example, a body of lead cooled to 7.2 degrees Kelvin suddenly drops to zero resistance.v The temperature at which superconductive materials undergo such transition is dependent on the magnetic field about the material. The critical temperature of 7.2 K. for lead supposes a zero magnetic field. As the field increases toward approximately 800 oersteds the transition temperature drops toward zero, and at intermediate temperatures there is a field which, if exceeded, will cause the lead body to change from superconducting state to a state of finite resistance. Thus for any given temperature below critical temperature there is la predetermined value of magnetic field above which lead undergoes transition from the superconducting state, and the transition between superconduction and finite resistance can be effected by varying the m-agnetic field respectively below and .above the predetermined value. Above the critical temperature no reduction of field can restore superconduction. Herein the term superconductive is used to designate the capabilityof the body to change between theabove-mentioned states, while super- Yconducting or superconduction designates the zero resistance state.

vIn an article, The Cryotron-A Superconductive Computer Component, Proceedings of the I.R.E., vol. 44, No.

4, April, 1956, I have described a superconducting device` comprising a length or gate of superconducting material, such as tantalum, on which is wound a control coil for applying a magnetic field to the gate. When the gate is below its critical temperature a sutiicient current through the coil will apply a magnetic field greater than the predetermined value and change the gate from superconducting, zero resistance state to a state of finite resistance.

Correspondingly, current through the gate will encounter either zero resistance or a finite resistance, and thus the cryotron gate acts as a valve.

One object of the present invention is'tof'provide a novel memory unit utilizing the peculiar characteristics of a Cryotrongate.

According to the invention an electrical memory comprises current-supply means and current-collection means, superconductors forming atleast one pair of alternate paths between said currentV means, variable impedance means in each path, input means for maintaining one of said impedances in each pair relatively high and one rela? tively low, interrogation means for introducing impedance alternatively into paths of a pair whereby when said input means and interrogation means establish impedance in both paths of a pair ofrelatively high impedance appears acrosssaid current means.

For the purpose of illustration typical embodiments of the invention are shown in the accompanying drawings in which FIG. 1 is a plot of transition temperature against -magnetic field applied to various superconductive elements; FIG.2 is a similar plot illustrating transition of a superconductive body between states; l

FIG. 3 is a block diagram of a memory unit;

FIG, 4 is a schematic diagram of the memory unit;

'FIG 77is a block diagram of amemory matrix em,

bodying a plurality of units; and

FIG. 8 is a schematic diagram of the memorymatrix.

As shown in FIG. 1 various elements are capable of superconducticn, depending upon the temperature and magnetic field of their environment. In this figure are shown the transition curves of aluminum (Al), thallium (Tl), indium (In), tin (Sn), mercury (Hg), tantalum (Ta), vanadium (V), lead (Pb) and niobiu-m (Nb). For each of these elements the curve is a plot of the transition temperature as a function of the applied magnetic field. Below the curve the element is superconducting, and above the curve the element has a finite resistance usually less than the resistance at room temperature.

As shown in FIG. 2 the transition curve is the boundary between the superconducting region and finite resistance region of a given element. For a given temperature environment T there is a predetermined magnetic field value H at the transition point or zone. Increasing the iield above the predetermined value H' destroys superconduction, while reducing the field below the predetermined Value establishes superconduction.

In FIG. 3is shown a superconductive memory unit including a cryotron flip-flop `F1 having having two output control coils Ctland C1 wound on the two arms G0, G1 of a superconductor connected between two current buses W1 and W2. A second superconductor G10-G11 between the buses is connected to the first by a superconducting crossarrn X. From a primary, constant current source I. current may iioW to the current-supply bus W1 through the superconductors G0, G1, X, G10 and G11 along one of two paths P1 or P2 to the current-collection bus W2. Preferably the buses W1 and W2 are superconductors. The arms G10, .G11 of the second super- Vconductor are embraced respectively by interrogation control coils l0 and I1 each of which is n series with a source of interrogation current Ii and an interrogation vswitch Si having contacts i0 and i1. Thecircuit W1, G0,

ditions by a set switch Ss having terminals s0 and s1 for setting a 0 condition or a 1 condition, the set switch being connected to a source of set current Is. It will be understood that the set `switch is symbolic of any signal source capable of applying a pulse to the s0 or s1 terminals.

When set current is supplied to one or the other of the set terminals, the flip iiop assumes a stable condition in which current flows either through control C0 or control C1. In 0 condition, for example, current in control C0 applies a field greater than the above-mentioned predetermined field, thereby changing arm G0 from zero to finite resistance. Since the iiipfiop will hold its 0 condition, the primary digit, or bit, 0 is stored in the H- shaped circuit. Alternatively the bit 1 can be stored by applying a magnetic field to arm G1.

To interrogate the memory unit, the interrogate switch Si is thrown to contact s0 or s1, thereby causing either control coil I0 or I1 to change gate G10 or G11 to resistive state. Assuming bit 0 to be stored and gate G0 in resistive state, interrogation whether bit l is stored, by making G11 resistive, will leave'a zero resistance path P2 through gate G10, crossarm X and gate G1. A vo1tmeter V will then indicate no resistance between the buses W1 and W2. However, if bit 0 is interrogated by changing gate G to resistive state, a finite resistance across the buses Will be indicated on the voltmeter V. Conversely, if bit 1 is stored and bit 0 interrogated, a zerofrlesistance.,-pathP'l remains acrosthe buses. g `But if bit l is stored and interrogated, gates G1 and G11 interposea'iinite resistance.r

In FIG. 4 'the nip-nop ensuit', while not by risen a Y part of the vpresent invention, is shown in Yconnection with Vthe H-shaped memory unit. A current source If supplies -ipdiop current through gates G4 and G5 respectively, totransferf control coils kT7 and T6 embracing gates G7 and G6: If current is established through gate G4, for example, -such current will kflow through transfer coil T7, thereby `applying a magnetic field to gate G7 and-blocking current iiow through Agate G7 and therefore G5. The'iiipf-flop is then in a stable condition in which-the established current flow through the ipop voutput control coil C1. Conversely if current is rst established in the fpath including gate G5,` transfer coil T6'and output coil C0, no current will flow in the path including gate G4 and coils T7 and C1. Current is set` orestablished through gater G4 or G5 by means of a. magnetic field applied by set coil `Stb or S1.

source of set lcurrent Is supplies current by transfer of l a switch Ss to one of two set contacts s0 or s1. After flipeopcurrent is set in one or the other of the described paths, `the "set .current vrmay be discontinued. Prior to settingthelcurrent, one or both of two enable gates?A GZ and G3 must be placed vin resistive state by Vcurrent through. enable '.cils E0' 'and El. ACurrent for the enable coils E0 and El, which may comprisea single coil, is

suppliedfrom a source Ie through a switch Se, a contact e and a conductor E. If these gates are superconducting prior to setting the iiip-iop, they act to shunt fromr its source lf'iiip-op current which otherwise tends tofow through one ofthe transfer coils T6 or T7;

For example if, with theenable switch Se open,

Hip-flop current Ifrto the superconducting path through gate-G5. Part ofrthis current owsvin a path through' gates G3, G2, E0, G6 and coils l'T7 and C1, while the the Y set switch Ss is thrown to contact s0, supplying current torcontrol coil C, gate -G4 is maderesistive and -diverts Ywidthwill cause a change of current Vthroughthe'priv mary T1 which will be amplified in the secondary TZ.V

remainder Vof theflip-op current owingthrough gate Y o G7 and coils T6 andCtl is insufficient to 4make gate G6 v 'resistive and assure a particular stable condition, How- Y ever, if` the `ena-bleswitch/"Se is closed, gates G2 and G3 are Ymade resistive and all rthe 'flip-flop current v4flows through the transfer coil T6 thus yestablishingthe stable condition preyiouslyfdescribed.

As shown Vin-jFIGf. 5 the-storage circuitmay comprise twoparallel Varms Gti. and G1" extending` between the buses; Wl and W2. YThe respective paths formed bythe ar'rnsG and G1 are controlled'by the output coils Ct) and C1 of the "flipsop F1. A set signal applied to theinput terminals si? and s1 of the p-opwill set condition 0 or l by control of the arm G0" or G1 causing it Jt'o become resistive.l With arm G0 resistive, for lex- L arm'lfGlT'and no resistanceV will exist between the buses W1, and Wlf If now, the memory is interrogated for l by` throwingl vthe interrogation switchV Si 'to Contact il,

additional resistance inV arm Gti is established by thev coil 11, .but arm Gl" remains super-conducting.; If, however, the interrogation is 0, the same bit as was set, coil iti makes gate Glresistive. Both'arms G6 and G1" being resistive, primary current is diverted to the control coil Cx oan output gate The diverted currentilowing through the output coil Cx Vappliesia held highernthan critical to the gate'Gx causing it .to become resistive. The 'establishmentof resistance in '-gate Gx may be Idetec'tedbya voltmeter, for thevgate may be used After interroga-tion,

to control 'current' lothercircuits. o current established f 'through the'- superc'onductr forming the 4output coil Cx Will continue even after gate G0" or ample, all current :will iiow through the superconducting several words are connected in series betweena set'cur-v parallel series.

G1 return to superconducting state. Therefore a control coil Q is provided for quenching such establishedcurrent. A short pulse applied to coil Q after interrogation will redivert the primary current 1 to the memory gates GG and G1". y

In FIG. 6 is shown an alternate ycircuit'for indicating the'presence of stored information. Two H-shaped circuits `X, Gil-G1, G10-G11', and X', GtlGl, G'10-'G11 are connected betweenbuses W1 and -WZ to which valternating current is applied `by a generator A whoserfrequency islfor examplefl to kilocycles per second."

Between the buses lis connected the primary T1 of a transformer whose secondary T2 is connected Lto an alterv mating current voltmeter Vac.

Assume the binary number 00 to be stored byA establishing resistance in arms G0 and G0. Alternating cur-V rent will now be -distributed among' the remaining superi conducting paths anda voltage will not appear Yacross the transformer primary. If the Vtwo digit memory is now asked if 00 is present by establishing resistance in arms Glu and G10, resistance will then 'appear in all armsV of the memory, diverting'current to the transformer primary T which may be superconducti've or resistive wire.

If a superconductive primaryis used, a quenching coil Q, y

may be substituted for the alternating current source A,y Y

iffthe interrogation signal hasV` a leading edge rwith a bandwidth approximately that offthe transformer.

terrogation pulse with a leading yedge Within that banda As shown in FIGS. 7 and 8 the memory circuits of FIGS. 3 to 6.are particularly well adapted as one :unit

or location in a large memory matrix. Whilethe H4 shaped storage unit of FIGS. 3, 4 and 6 is illustrated,r

the unit GlV-Gl of .FIG 5 may also be used. Y

The matrix comprises 1a plurality of units arrangedin resents Va numerical word having n' digits. The top series or word f1 includes locations 11, 12 to 1n, thek second series or Word 2 includes locations 21, 22 to 2N, and

so on to the last'se'ries, word VN with locations N1, N2' Y to Nn.Y YFor convenience, the iirst digit lofeach location identities the word, and thesecond digit identifies thebit of a word. For example, Vlocation 12 representsbitV 2 of word l. the like numbered locations. A ssource of primary current I' is connected vacross the buses W1, W2 to Wir-H whichare `interconnected :by 'the ystorage units ofthe several locations. Y Y Y For each word, theenable'conductor is Vra single ywire E extending from a terminal e successively through each V location of the word. Flip-flop current is supplied from a source If throug'hconductors :F connecting `all the ,flipilops of each word in series. l

The set coils S0` or,r S1 forfthe 1st,'2nd or4 nth digitof rent supply Is `and set terminals s0 and s1 respectively. Similarly the kinterrogatecoils I0 or`I1 are connected in series with 'interrogato terminals t0 or` i1.

each word may be enabled byl supplying enablefcurrent to the terminal e for that word. Iny contrastv thesame,

e.g'. `nth,'1ocation of vallword's is supplied with set currentY alternatingV cur- Y o Forv examplegif the transformer T1-T2 has a bandwidth of 50 cycles per second to 2() kilocycles per second, an in- Each horizontal series of location repl Flip-flops yF11 to FNn areassociated withv from one pair of set terminals .t0-S1. AFor example, to set the bit one in location 12, the enable terminal e for word l vis energized, and simultaneously 'the terminal i1 for the 2nd location of all words is supplied with set current. Words 2 and N, not being enabled, will not be aiected by current through their set coils. However, word 1, bit 2, being both enabled and set, will store the digit l by control of its gate G1 as described with reference to FIG. 3. By successively energizing the several pairs of set terminals .v0-s1, bits one or zero may be stored or written in each location of a word. The words are written successively, by progressive energization of the several enable terminals e.

f All the words of the memory matrix of FIGS. 7 and 8 may be interrogated simultaneously by simultaneous supply of current 'in steady or pulse form to all the pairs itl-i1 of interrogate terminals.

For example, suppose that the code information 100, 110 and lll are written in words l, 2 and N, bysetting the digit one in location 11, the digit zero in location 12, the digit zero in location 1N and so on. Further suppose that the memory is first asked whether 000 is stored, and second whether 100 is stored.

On the first interrogation, 000, some of the paths between the buses will be resistive since both gate G0 and gate G10 will be held in resistive state respectively, by ip-flop control and interrogate coil control. However, they first digit of each word, for example, will have gates G0 and G11 in superconducting, zero resistance state, so that no voltage drop appears between any adjacent two buses W1, W2, etc.

On the second interrogation, 100, gates G1 yand G11 of location 11 and gates'G0 and G10 of locations 12 and 1n will be resistive, so that in general word l of the memory is resistive and a finite resistance exists between buses W1 and W2. With separate voltmeters V1, V2 and V3 connected across adjacent pairs of buses, as shown in FIG 7, voltmeter V1 will register a finite resistance indicating that theinterrogated word l0() is stored in the locations of word 1 of the memory.

1f, asshown in FIG. 8, only one voltmeter V is connected between bus W1 and Wn-i-l, the establishing by interrogation of resistance in-all the locations of a word places a resistance across oney adjacent pair of' buses but notV across the other buses of the matrix. Still a resistance will exist across buses W1 and Wn-l-l. Accordingly, the meter V will indicate that the interrogated word is stored in the matrix, but will not identfiy the location in which it is stored. i

It should be understood that a superconductive wire such as the superconductor G0 between bus W1 and crossarm X `comprises both a circuit Vconnection there between and a cryotron value or variable impedance at the portion on which the control coil C0 is wound.

It will further be understood that the present invention includes other modifications and equivalents falling within the appended claims.

I claim:

1. An electrical Vmemory comprising lcurrent-supply means and current-collection means, superconductors forming at least one pair of alternate magnetically independent paths between said current means, yvariable impedance means in each path, input means yfor maintaining one of said impedances in each pair relatively high and one relatively low, and interrogation means for introducing impedance alternatively into paths of a pair, whereby when said input means and interrogation means establish impedance in both paths of a pair a relatively high irnpedance appears across said current means.

2. VAn electrical memory comprising current-supply means and current-collection means, superconductors forming at least one pair of alternate magnetically independent paths between said means, output terminals at the common ends of said paths, variable impedance means in 6 pedances in each pair relatively high and one relatively low, and interrogation means for introducing impedance alternatively into the paths of a pair, whereby when said input means and interrogation means establish impedance in both paths of a pair a relatively high impedance appears across said output terminals.

3. An electrical memory comprising current-supply means, current-collecting means, superconductive means forming two magnetically independent paths Vbetween said means, said superconductive means being responsive to a predetermined magnetic field to change between a zero resistance state and a state of iinite resistance, for each path a iirst control means yfor applying a magnetic `lield to said superconductive means, and for each path second control means for applying a magnetic tield alternatively to said respective paths whereby when one path is held in nite resistance state, such conditions can be identified by the application by said second control means of a magnetic field to the other path, thereby to establish a .finite resistance between said current-supply and current-collection means. f

4. An electrical memory comprising current-supply means and current-collection means, superconductors forming at least one pair of alternate magnetically independent paths between said current means, variable i-mpedance means in each path, input means for maintaining one of said i-mpedances in each pair relatively high and one relatively low, interrogation means for introducingrimpedance alternatively into paths of a pair, whereby when said input means and interrogation means establish impedance in both paths of a pair a relatively high impedanceappears across said current means, and output means Connected across said current means to which current is diverted when said high impedance appears across said current means.

5. An electrical memory comprising current-supply means, current-collecting means, superconductive means forming two magnetically independent paths between said means, said superconductive means being responsive to a predetermined magnetic field to change between a zero resistance state and a state of nite resistance,V for each pathilnput control means for applying a magnetic field to f said superconductive means, write-in means for establishing current alternatively in the input control means for one path of a pair thereby to change said one path to finite resistance state, for each respective path of a pair interrogation control means for applying a magnetic field alternatively to one of said respective paths, whereby when one path is .held in finite resistance state by said write-in means, such condition can be identiiied by the application by said interrogation control means of a magnetic field to the other path thereby to establish a finite resistance between said current-supply and current-collection means, and means for indicating said identity comprising a conductor connected between said current means to shunt said paths, said conductor including electromagnetic output means, whereby when said paths are resistive, current is diverted from said paths to said conductor thereby to energize said electro-magnetic output means.

6. An electrical memory according to claim 4 wherein said output means comprises an electromagnetic device.

7. An electrical memory according to claim 4, wherein said output means comprises a transformer primary.

8. An electrical memory according to claim 4 wherein said output means comprises a cryotron including a superconductive gate and a control therefor connected between said current means in series with a cryotron.

9. An electrical memory according to claim 4 characterized by an indicator connected to said output means.

10. An electrical memory comprising at least three parallel current-supply means and current-collection means, conductors forming a plurality of pairs of alternate paths between adjacent pairs of said current means, variable impedance means in each path, input means for each path, input means for maintaining one of said` immaintaining one of said impedances in each pair relatively means.

t, Y'2?'. high and one relatively low, interrogation `means forl introducing impedance alternatively into Ypaths of a pair, Vwhereby'when said input Vmeans and interrogation means establish impedance-inf both pairs of a pair a relatively high-impedance `appears across said current means, said interrogation meanscornprising-at least one conductor vdisposed to control paths between two pairsfof said current means. t

1l. An electrical memory A.comprising at least three parallel current-supply `means and current-collection means', super-conductors forming a plurality of pairs of alternate paths between adjacent pairs 4of said current means, variable impedance meansin -f each path, input means for maintaining onefof said impedances in each pair -relativelyhigh and one relatively -low, linterrogation rneansfor introducing Vimpedance alternatively into `paths of a pair, whereby when said" input'means and interrogation means" establish vimpedance inl both paths of a pair a relativelyhigh impedance appears Hacross said current means, said interrogation means-comprises a plurality of electromagnetic means respectively controlling a superconductor in on'e'path of each of said pairs of paths, said electromagnetic means being connected in a series, so k that a plurality of pairs may ybeinterrogated simultaneously,

Y lZJAn electrical memoryV comprising current-supply means, current-collecting means, superconductive means forming a plurality of pairs of paths between said-means, said superconductive 'means Vbeing responsive toV a pre- 1 determined magnetic tield fto change between a zero resistance state and a state of iinite resistance, for leach path-of `a pair ra first 'control means'for' applying a magnetic tield to said superconductive means, bistable means .for establishing current alternatively in said first control means thereby to changeone of said paths to finite resistancye state, foreach path second control means `for ap.-

i pplyingV amagnetic iield alternatively to said respective paths, whereby when one path of each pair is held in yfinite resistance ,state by said bistable means, such condition can be `:identified by the application by said second control means 4of a magnetic field to the other path of each thereby to establish a finite resistanceV between said current-supply and current collection means, `and an enable conductor connected to render-effective all bistable means controlling the pairs of paths between said current 13. electrical memory comprising current-supply means, current-collecting means, `superconductive means icrnriin'g a plurality of pairs of paths between isaidmeans, said superconductive means being responsive to alpredeterminedfmagnetic-field to changebetween a zero resistance" state and a state of finite resistanceffor each path of a pair a iirst controlV means jfor applying a magnetic `tield tofsaid superco11d.ic'tive ine'ans, bistable means forI establishinfr current alternatively in onefirst control means for a pair therebytoc'hange one path of a pair toffinite resistance state, for each `respective path of a pair second control means for applying a magnetic field alternatively A Vto said respectivepaths, whereby when one path of each pair is held in finite resistance state by said bistable means, such condition'can be Videntified by the application 'by said second controlmeansof a magnetic fleldto the other patho each thereby to establishV a finite resistance between saidcurrent-supply and'current-collection means, each-of said-bistable means'comprising a set cryotr'on, a superconductive shunt in parallel therewith to disable vthe cryotron, andan electromagnetic control'means for Ythe shunttto enable saidsetcryotromiall yshunt control means for `pathsbetween said current means beingY connected in series, whereby all they cryotrons of the bistable meansV may be?enabledsimultaneously.

14. A superconductive electrical 'memory' comprising atleast three `current-supply and current-collectionmeans,

between neach-.adjacen't two current,i means a pluralitycf locations each :location .comprising superconductors" ;or1

CTI

' least three 'current-supply and :current-collection means,.v

cludingtwo/output'inductive means `disposed alternatively to lapply said predetermined. magnetic eldtosuperconductors in said respective paths, '-said locations formingla -word-s'eries'between .each adjacent pair of Icurrent means and av'place-scries eXtendingthroughthe sarnebit of eachv of :'the several word-series', .interrogation means comprising two interrogation inductive means for each location, -eachinterrogation inductive .means controlling one path-of each "loca-tion,Y andfone.y induction means of each `interrogation meansin a place-series being connected Yin series with one inductive means Aof each other interrogation inductive means infthe sarneserie's,1so that the same location fof all words may`=be interrogatedvsimultaneously. l Y

Y 15 A superconductive'electrical memory icomprisingrat between `each adjacent two current means ka pluralityI of locations, each location-comprising superconductorsilconnected between `said-two current 'means and'for'ming a pair of superconductivepathssaid superconductorsbeing responsive-to a predetermined magnetic field to change from-superconducting, 'zero resistance state to' aY state of finite resistancejforeach vlocationa bistablefdevice including two output "inductive: means'disposed alternatively `to .apply said ypredetermined magneticeld to superconductors in said respective paths, and said device'including-two set cryotrons for selecting one of said output inductive means, and a shunt Acryotronit'or kdisablingsaid set cryotrons,` said locations forming a word-series 'betweeneach adjacent pair of current means :and a place-series extending-throughv the 'same bit ofeach of the several i Word 'series,\ the shuntV cryotro'nsfor--all"locations oi` a word-seriesbeing connected'in'seriesand one set rcryotron of a place-series" being connected -in series with `one ,set cryotron'for the same bit'in each' other' WOYLSOV ihat a single location may beV selected by'applyinglcurrent to enable cryotrons of one word and the set leryotroneof one place-series, interrogation mean's'comprising two in- Y terrogation inductive. `means for? each location, Veach-r interrogation inductive means controllinggonepath'.ofeach location,"'and one inductive'means of Veach interrogation vmeans in aplace-series beingconnectedin'series with t one inductivemeans "of leach other interrogation inductive Y means in the same series, so that'the 'same location gof Lallwords-may be interrogated simultaneously.

j 16. A cryotronl catalog-memory `comprising current- A.supply and current-collection means, superconductive meansjforming -at least threekmagnetically Yindependent paths between said currentjmeans, means for-'rendering resistiveV each of said paths, and a single means connectedto detect the presence or absence of superconduction f in all of said paths simultaneously-between said current l means. j

17.Acr`yotr'on catalog memorycomprising .currentsupply and l current-collection means,V superconductive meanspforming a plurality of magnetically independent paths between'said current means, said superconductive means `being'responsive to a predetermined'el'd :to'change between a zero resistancestate and a state ofiinite resistance, interrogation meansV for' rendering resistive each of said paths, and a Vsingle means connected-to rlet'ect'theV presence `or absence :of superconduction in all of said paths lsimultaneously between -said current means, each of said paths having atleast one storage location and at least oneV of 'said locations being resistive prior to operation'of said'rendering means, lsaidA rendering meansbeinglcapa'ble of lrenderingv -all *the remaining Vlocations resistive. i

A cryotron cataloglmemorycomprising current- -supply .and current-collection means, superconductive sparire means forming at least three magnetically independent` paths between said current means, said superconductive means being responsive to a predetermined eld to change between a zero resistance state and a state of finite resistance, a plurality of conductors for carrying current and disposed to apply said predetermined field to each of said paths, and a single means connected to detect the presence or. absence of sup'erconduction in all of said paths simultaneously between said current means.

19. A catalog cryotron memory comprising at least three `superconductive current means including currentsupply and current-collection means, superconductive p means forming a plurality of magnetically independent paths between adjacent pairs of said current means, means for rendering resistive each of the paths, and means for detecting the presence or absence of superconduetion in said paths between said current means.

20. A memory according to claim 19 wherein said detecting means is connected to detect the presence or absence of superconduction between the tlrst and last of said current means. Y

21. A memory according to claim 19 wherein said rendering means comprises a plurality of control conductors disposed to apply magnetic fields to selected paths.

22. A memory according to claim 19 'wherein a. single control conductor is disposed to apply a magnetic eld to paths between at least two adjacent pairs of current means. l

23. A cryotron catalog memory comprising a plurality of superconductive gate paths connected in parallel to form -a composite conductor, a source connected to pass an electric current through said composite conductor, a plurality of control current paths, each of said control paths being in relatively close magnetic proximity to a plurality of portions of gate paths, whereby current through a control path may render resistive the gate portions in close proximity thereto to the exclusion of the remaining gate path portions, and output means responsive to the presence or absence of superconductivity through said composite conductor.

References Cited in the file of this patent UNITED STATES PATENTS Buck Apr. 29, 1958 OTHER REFERENCES 

